1. Field of the Invention
The present invention relates to an etching method used in a method of manufacturing a semiconductor device, and more particularly, a method of dry etching an SiC film and a method of manufacturing a multilayer wiring structure using an SiC film.
The present application is based on Japanese Patent Application No. 295905/2000, filed on Sep. 28, 2000, the contents of which is incorporated herein by reference.
2. Description of the Related Art
As semiconductor device elements become smaller, it is essential to form smaller multilayer wiring for the semiconductor device. In addition, as the semiconductor device is operated at a lower voltage, a higher speed, or the like, it is necessary to form an interlayer insulating film having a lower dielectric constant.
More specifically, in a semiconductor device of a logic system, increased resistance due to smaller wiring and increased parasitic capacitance between wirings results in a reduction of the semiconductor device operation speed. Thus, it is essential to form a small multilayer using a low dielectric constant film as an interlayer insulating film (e.g., a silisesquioxane such as hydrogen silsesquioxane, hereinafter referred to as HSQ) as an interlayer insulating film with a low dielectric constant.
The small wiring width and short wiring pitch result in an increase in the aspect ratio of the wiring and an increase in the aspect ratio of a space between wirings. As a result, techniques for forming a strip of minute wiring longitudinally and embedding an interlayer insulating film in a space between minute wirings become more difficult. Thus, the related art semiconductor device manufacturing process is complicated, and the number of subprocesses in the related art manufacturing process increases.
In the related art system, a groove wiring technique (i.e., a damascene technique) forms a wiring groove in an interlayer insulating film and embeds a wiring material such as copper (i.e., Cu) in the wiring groove by using chemical mechanical polishing (hereinafter referred to as CMP). However, when a wiring groove or a via hole is formed by a reactive ion etching (hereinafter referred to as RIE) process, it is necessary to form an etching stopper layer.
The etching stopper layer is an insulating film with an etching speed different from that of an interlayer insulating film where the wiring groove or the via hole is formed. Various related art techniques using an insulating film with a low dielectric constant as the inter layer insulating film and using a silicon nitride film (SiN film) or a silicon oxide nitride film (SiON film) as the etching stopper layer have been proposed. For example, but not by way of limitation, Japanese Patent Application Laid-open No. Heisei 10-116904 and Japanese Patent Application Laid-open No. Heisei 10-229122 disclose related art manufacturing techniques.
FIGS. 1A to 1C illustrate cross sectional views of a related art manufacturing process of a dual damascene structure. As shown in FIG. 1A, a copper lower layer wiring 101 is formed over a semiconductor substrate (not shown) via an insulating film. Then, a SiN film 102 is formed to cover the copper lower layer wiring 101.
Next, an interlayer insulating film 103 is deposited on the SiN film 102, and the surface of the interlayer insulating film 103 is leveled by CMP. The interlayer insulating film 103 is a silicon oxide film formed in plasma by using a chemical vapor deposition (hereinafter referred to as CVD) method.
Next, using a related art photolithography technique and a related art dry etching technique, a via hole 104 that reaches the surface of the SiN film 102 is formed in the interlayer insulating film 103. Further, a wiring groove 105 is formed in the interlayer insulating film 103. After the via hole 104 and the wiring groove 105 are formed, a resist mask used as an etching mask is removed by using a related art ashing method that ashes the resist mask as an organic film with an oxygen plasma. In the related art ashing process, as shown in FIG. 1A, the copper lower layer wiring 101 is protected by the SiC film 102. Therefore, the copper lower layer wiring 101, which is otherwise easily oxidized, is not exposed to the oxygen plasma, and is protected from the oxidation.
Next as shown in FIG. 1B, using the interlayer insulating film 103 as an etching mask, the SiN film 102 is dry-etched by RIE to form a via hole 104a that reaches the surface of the lower layer wiring 101. The dry etching of the SiN film 102 is performed by introducing a gaseous mixture of CH2F2, O2, and Ar into a space between parallel plate electrodes. The gaseous mixture is then plasma-excited with a high frequency energy of 13.56 MHz, which is applied between the parallel plate electrodes. In the dry etching step, a ratio of an etching rate of the SiN film 102 to that of the interlayer insulating film 103 (i.e., a selection ratio) is about 3 to 5, and the film thickness of the SiN film 102 is about 50 nm.
As illustrated in FIG. 1C, after a thin tantalum nitride (TaN) film and a copper film are laminated, the lamination film is processed by CMP, so that a barrier layer 106 and a groove wiring 107 are formed in a predetermined region of the interlayer insulating film 103. The barrier layer 106 and the groove wiring 107 are electrically connected to the copper lower layer wiring 101. By the above related art processes, the related art dual damascene wiring structure can be obtained.
However, the related art as described above has various problems and disadvantages. For example, but not by way of limitation, since the dielectric constant of the etching stopper layer increases, the parasitic capacitance between the copper lower layer wiring 101 and the upper layer wiring 107 in the multilayer wiring structure increases. In addition, a parasitic capacitance between wirings of the same layer increases due to a fringe effect generated between wirings of the same layer through the SiN film 102.
Further, in the above described example, a relative dielectric constant of the SiN film is 7 to 8. If the interlayer insulating film is formed using an HSQ film with a relative dielectric constant of about 3, the parasitic capacitance at least doubles. Thus, the operation speed of the semiconductor device (more specifically, a logic system of a semiconductor device) is reduced. Alternatively, since a groove wiring cannot be formed using a low dielectric constant film as an interlayer insulating film, there is a limitation on a low dielectric constant of the interlayer insulating film.
It is an object of the present invention to provide a simple etching method in which a low dielectric constant film can be effectively used as an interlayer insulating film and to reduce parasitic capacitance between groove wirings, by easily performing dry etching of an SiC film.
It is another object of the present invention to shorten a manufacturing process and reduce a manufacturing cost of a semiconductor device.
To overcome the aforementioned related art problems and to achieve at least the aforementioned objects, a method of etching a silicon carbide film is provided, comprising forming a silicon carbide film on a semiconductor substrate, and etching said silicon carbide film with an etching gas that comprises a halogen compound and a nitrogen containing gas.
Additionally, a method of manufacturing a semiconductor device is provided, comprising (a) forming a wiring on a semiconductor substrate, (b) forming a silicon carbide film on said wiring, (c) forming an interlayer insulating film on said silicon carbide film, (d) etching said interlayer insulating film to form a via hole by a first etching gas, and (e) etching said silicon carbide film that is exposed in said via hole, by a second etching gas comprising a halogen compound and a nitrogen containing gas.
Further, a method of manufacturing a semiconductor device is provided, comprising (a) forming a wiring on a semiconductor substrate, (b) forming a first silicon carbide film on said wiring, (c) forming a first interlayer insulating film on said first silicon carbide film, (d) forming a second silicon carbide film on said first interlayer insulating film, (e) forming a second interlayer insulating film on said second silicon carbide film, (f) etching said second interlayer insulating film an d said second silicon carbide film, and then etching said first interlayer insulating film to form a via hole by a first etching gas, (g) etching said second interlayer insulating film to form a wiring groove by using said first silicon carbide and said second silicon carbide as an etching stopper, and (h) etching said first silicon carbide film exposed in said via hole by a second etching gas comprising a halogen compound and a nitrogen containing gas.
Therefore, according to one embodiment of the etching method of the present invention, in a dry etching of an SiC film used in manufacturing a semiconductor device, a gas containing nitrogen is added to an etching gas containing a halogen compound. Such a halogen compound is a fluorine compound. The fluorine compound is fluorocarbon, nitrogen trifluoride (NF3), or sulfur hexafluoride (SF6). The fluoro-carbon is CF4, CHF3, CH2F2, CH3F, or C4F8. Here, an oxygen gas may be mixed with the etching gas containing the fluoro-carbon.
Alternatively, according to the etching method of the present invention, in a dry etching of a lamination film of an SiC film and an interlayer insulating film which is made of, a silicon oxide film used for a semiconductor device, a silsesquioxane insulating film, or a silica film including at least one bonding of an Sixe2x80x94H bonding, an Sixe2x80x94CH3 bonding and an Sixe2x80x94F bonding, a gas containing nitrogen is added to an etching gas containing a halogen compound, which is used in dry etching of the interlayer insulating film in the dry etching of the SiC film.
Then, the gas containing nitrogen is a nitrogen gas, an ammonia gas, or a nitrous oxide gas. An end point detection in the dry etching of the SiC film is performed by measuring an light emitting intensity in a wavelength of 387 nm from a reaction product CN.
According to the etching method of the SiC film of the present invention, the added nitrogen is plasma-excited and then chemically bonded to carbon (C) of the SiC film as a material to be etched, so that a reaction product CN with a high volatility is formed. Thus, the dry etching of the SiC film, which is difficult until now is very easy.
Alternatively, a method of manufacturing a semiconductor device, according to the represent invention is a method of manufacturing a multilayer wiring structure, including the steps of: forming an SiC film for covering on a lower layer wiring; forming an interlayer insulating film for covering the SiC film, and forming a via hole which reaches a surface of the SiC film and a wiring groove connecting with the via hole by dry-etching a predetermined region of the interlayer insulating film; removing the SiC film exposed in a region of the via hole by etching using the interlayer insulating film as an etching mask such that the via hole penetrates the SiC film to the surface of the lower layer wiring; and filling the penetrating via hole and the wiring groove with a conductive material to form a groove wiring connecting with the lower layer wiring, and removal of the SiC film by etching is performed by adding the gas containing nitrogen to the etching gas containing the halogen compound.
Alternatively, a method of manufacturing a semiconductor device, according to the present invention, is in manufacturing a layer wiring structure, a method of manufacturing a multilayer wiring structure, including the steps of: forming a first SiC film for covering on a lower layer wiring; forming a first interlayer insulating film, a second SiC film, and a second interlayer insulating film in this order on the first SiC film; dry etching the second interlayer insulating film, the second SiC film, and the first interlayer insulating film in succession to form a via hole which reaches a surface of the first SiC film; dry etching a predetermined region of the second interlayer insulating film using the second SiC film as an etching stopper layer to form a wiring groove connecting with the via hole; after the formation of the wiring groove, removing the first SiC film exposed in a region of the via hole using the second interlayer insulating film as an etching mask such that the via hole penetrates the first SiC film to the surface of the lower layer wiring; and filling the penetrating via hole and the wiring groove with a conductive material to form a groove wiring connecting with the lower layer wiring, and removal of the SiC film is performed by adding the gas containing nitrogen to the etching gas containing the halogen compound. Here, the second interlayer insulating film may be made from two layers to be laminated of different kinds of insulating films.
Then, the interlayer insulating film, the first interlayer insulating film, or the second interlayer insulating film is made of a silicon oxide film, a silsesquioxane insulating film, or a silica film including at least one bonding of an Sixe2x80x94H bonding, an Sixe2x80x94CH3 bonding and an Sixe2x80x94F bonding. Also, the silsesquioxane insulating film is hydrogen silsesquioxane, methyl silsesquioxane, methylated hydrogen silsesquioxane, or fluorinated silsesquioxane. Further, the lower layer wiring or the groove wiring is made of copper (i.e., Cu).
As described above, according to the present invention, the dry etching of the SiC film is easily performed, and the SiC film can be easily applied as a stopper layer in manufacturing of a multiplier wiring structure such as a dual damascene structure. Thus, a parasitic capacitance between a lower layer wiring and an upper layer wiring in the multilayer wiring structure is reduced, and a parasitic capacitance between wiring layers of the same layer due to a fringe effect generated between wirings of the same layer is largely reduced. Further, a low dielectric constant film can be effectively used as an interlayer insulating film, and a parasitic capacitance between groove wirings can be reduced.
Also, a lamination film of the interlayer insulating film and the SiC film, constituting a semiconductor device, can be processed by etching using a simple method. In addition, a manufacturing process is shortened and a manufacturing cost of a semiconductor device is reduced.